1. Field of the Invention
The present invention refers to a circuit board, especially to a circuit board with an improved timing characteristics of different signals in a data bus.
2. Description of Prior Art
Often it is a topological problem in computer technology, especially in computer subsystems and other devices to distribute a signal via a wide data bus from a first unit with very small pin pitch and/or dimensions to a second unit with a larger pin pitch and/or dimensions. Especially when the first unit is, for example, a processor, controller or the like and the second unit is, for example, a row of connectors, both being arranged on a circuit board, such a problem arises as the pins of the first unit has a small pin pitch and the second unit has a much larger pin pitch as to securely and tightly connect the row of connectors. FIG. 4 shows such an arrangement in which a controller with five pins (denominated c1, c2, c3, c4 and c5) has to be connected to a DIMM memory module also with five pins (denominated 1d, 2d, 3d, 4d and 5d). For the reason of simplicity only five lines are shown in FIG. 4, nevertheless a bus connecting the controller to the DIMM can comprise more than five lines as for example 64 data bus lines for 64 bits. Herein the memory controller has for example dimensions of approximately 25×25 mm and the memory controller should be connected via the 5 (respectively 64) bit wide data bus to the DIMM memory module there arises a problem in view of signal synchronization when the DIMM memory module is, for example, 135 mm long as roughly outlined by the vertical extension of the DIMM memory module in FIG. 4 in contrast to the dimensions of the controller. On the one hand, from synchronization point of view, delay in each bit line between the controller and the DIMM must be the same to provide an synchronous switching data transmission operation. On the other hand, this is very difficult to realize since, for example, pin c3 of the controller has a direct length to a pin 3d of the DIMM which is obviously shorter than a direct connection from pin c1 of the controller to pin 1d of the DIMM. In order to overcome this problem, conventional techniques use meandering structures to “artificially” enlarge the length of data bus lines for connections between pins of the data bus being located closer to each other than other pins of the data bus. In FIG. 4 such a meandering structure can be seen in the line connecting pin c3 of the controller with pin 3d of the DIMM. Furthermore, a connection between pin c2 of the controller to pin 2d of the DIMM as well as a connection of pin c4 of the controller to pin 4d of the DIMM also have meandering structures. However, the summary length of the meandered line is not that large as the amplitude of the meanders in the line connecting pin c3 of the controller to pin 3d of the DIMM as the distance between pin c2 of the controller to pin 2d of the DIMM is larger than the distance of pin c3 of the controller and pin 3d of the DIMM. As can be seen in FIG. 4 the connection line between pin c1 of the controller to pin 1d of the DIMM as well as the connection line between pin c5 of the controller to pin 5d of the DIMM has no meanders. By providing such a meandering structure in a data bus system, a synchronization of the signals outputted from the controller can be realized, such that the signals arrive at the pins of the DIMM exactly at the same time and thus compensating runtime differences among connection lines of the different pins of the controller and the DIMM. However, if a distance from the controller to the DIMM is small, then the central area between the controller and the DIMM will be occupied by trace serpentines (or meanders) and only traces on the edges of the bus will not have a meander structure. This can be clearly seen in FIG. 4 as the space 402 between the controller and the DIMM in the range of pins c2 and c4 of the controller and pins 2d to 4d of the DIMM is nearly completely filled with meander structures. As can be seen in FIG. 4, such meander structures require several iterations of the routing, and still consumes too much of area. In some cases additional PCB layers are required. However, even now such structures are routed manually in 90% of the cases.
Thus, as to improve routing characteristics for a memory data bus, a bus being 64 bits wide is usually divided by groups of 8, and timing as well as synchronization/length matching is done only inside this small groups and therefore the routing of the small group of traces can be carried out more easily with said meander structures. For a trace length matching a meandering structure is used normally.